Aspects of the present invention relate generally to integrated circuit designs, and in particular to techniques for simulation and test of such designs.
Integrated circuit (IC) design is increasingly complex, sometimes involving millions of elements, shapes or geometries, and may be facilitated with an electronic design automation (EDA) tool that allows a designer to interactively position (“place”) and connect (“route”) various shapes on the circuit. The EDA tool then creates a circuit layout containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design that may then be fabricated, creating the IC. The designed IC is eventually fabricated by transferring or printing the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit.
After or during the design and creation of an IC layout, validation, optimization, and verification operations are performed on the IC layout using a set of testing, simulation, analysis and validation tools. These operations are conventionally performed in part to detect and correct placement, connectivity, and timing errors. For example, as part of the verification, the IC layout may undergo circuit simulation and analysis, for example using harmonic balance analysis to calculate the periodic steady-state for circuits that include non-linear elements. Harmonic balance analysis is a method used to simulate circuits that include non-linear elements, for example mixers, power amplifiers, and oscillators, by calculating the periodic steady-state response of non-linear differential equations for the circuits. However, such calculations for a large and complicated circuit design often require a substantial amount of resources, including both memory and processing power. Designers often have to request access to special resources in order to complete the harmonic balance analysis. Unfortunately, the amount of memory the harmonic balance analysis will use is not known until the simulation is complete. On some occasions, if the designer does not request sufficient memory or processing power, the analysis will fail and many hours, sometimes days, of simulation will be lost. However, due to the high demand for these resources, designers are discouraged from requesting memory in excess of their requirements where requesting too much memory would leave such resources idle.
Accordingly, there is a need in the art for a system to provide an accurate estimate of the potential memory usage when planning computing resources needed during a harmonic balance analysis.